Borey Advanced ASMPT: The Core Solution for High Speed SiP Mounting
2025-08-04

With the accelerated development of intelligent trends, electronic products are constantly evolving towards smaller size and higher performance, and System in Package (SiP) has gradually become a key technology to achieve this trend. It effectively improves system performance by integrating IC chips and SMT components in a single package, while significantly reducing product size, and has become one of the key paths to advanced packaging.
However, in the face of complex packaging structures and increasing performance requirements, traditional SiP production lines usually need to complete two separate processes, SMT mounting and chip bonding, with multiple equipment types, complex operations, and fragmented processes. This not only increases production costs but also limits the flexibility and response speed of the production line.
To this end, ASMPT has launched SIPLACE CA2, which integrates SMT mounting and wafer chip mounting into one device, breaking the traditional segmented process and truly achieving "one machine can handle two processes", providing a more efficient, flexible, and forward-looking solution for SiP packaging mass production.

One machine handles two processes
SIPLACE CA2 integrates SMT and semiconductor mounting processes into a unified process, which can simultaneously handle SMD components on tape and bare chips directly taken from wafers. Its mounting speed can reach up to 50000 chips or 76000 SMD per hour, with an accuracy of 10 μ m @ 3 σ, greatly improving the flexibility, production capacity, and yield of the production line, especially suitable for various high-speed SiP production application scenarios.
SIPLACE CA2 not only supports multitasking with one machine, but also saves space and labor costs that originally required multi device collaboration. A highly automated chip buffer system can synchronously pre fetch chips during the mounting head operation, achieving parallel processing of wafer pickup and mounting, making chip processing efficiency close to traditional SMT pace, while significantly reducing production bottlenecks and line changing waiting.

The full process intelligence from chip to factory
SIPLACE CA2 not only has efficient wafer switching capability, with a fastest time of only 6.5 seconds and support for up to 50 types of wafers, but also helps customers save material costs, reduce waste, and enhance sustainability by directly processing bare chips, avoiding the ribbon weaving process.
At the same time, SIPLACE technology, with its comprehensive bare chip level tracking capability, can automatically record the pickup position of each chip and its placement position on the circuit board, meeting the compliance requirements of the high reliability industry.
Combined with ASMPT's WORKS software and standardized interfaces such as IPC-CFX and SECS/GEM, SIPLACE CA2 can be seamlessly integrated into MES and automated logistics systems, helping to build future smart factories.

A strategic platform for future packaging
Sylvester Demmel, Senior Product Manager of ASMPT SMT Solutions Department, summarized the strategic significance of SIPLACE CA2 as follows: "SIPLACE CA2 combines key capabilities of the SiP era and opens up new areas of advanced packaging. ”
By integrating SMT and chip mounting processes into a single process, SIPLACE CA2 not only helps customers meet the challenges of advanced packaging, but also opens up new market opportunities and customer groups for electronic manufacturers. While improving production capacity and quality, it effectively reduces operating costs and builds a new competitive advantage.
SIPLACE CA2 is the culmination of ASMPT's continuous technological accumulation in advanced packaging and intelligent manufacturing. It is not only a device upgrade, but also a manifestation of a new manufacturing concept - focusing on efficiency, green and intelligence, helping customers respond to technological evolution at a faster pace and with higher quality.
In this era of accelerated change in system level packaging, SIPLACE CA2 makes the goal of "future packaging" no longer distant.

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